Design and Characterization of a 5.2 GHz/2.4 GHz ΣΔ Fractional-N Frequency Synthesizer for Low-Phase Noise Performance

This paper presents a complete noise analysis of a ΣΔ-based fractional-N phase-locked loop (PLL) based frequency synthesizer. Rigorous analytical and empirical formulas have been given to model various phase noise sources and spurious components and to predict their impact on the overall synthesizer noise performance. These formulas have been applied to an integrated multiband WLAN frequency synthesizer RFIC to demonstrate noise minimization through judicious choice of loop parameters. Finally, predicted and measured phase jitter showed good agreement. For an LO frequency of 4.3 GHz, predicted and measured phase noise was 0.50◦ rms and 0.535◦ rms, respectively.